Hi folks,

Do HW breakpoints work in orpsoc2?

I am working with the RTL in orpsocv2.

This is what I see in or1200_du.v:

//
// Write to DCR0
//
`ifdef OR1200_DU_DCR0
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr0 = 8'h00;
else if (dcr0_sel && spr_write)
dcr0 = spr_dat_i[7:0];
`else
assign dcr0 = 8'h00;
`endif

Notice that the reset value of DCRn[0] (DP) is 0 whne a DCR is enabled. Shouldn't it be 1 if a HW breakpoints are enabled?

The adv_jtag_bridge hwp_server.c seems to use DCRn[0] (DP) to determine if a HW breakpoint is available.

Thanks,

John Pavan

Hi Folks,

I messed up.

I didn't notice that the adv_jtag_bridge project came with a HW breakpoint patch for the RTL. (or1200v1_hwbkpt.patch)

It's quite extensive.

I'll try to implement and test the patch and I'll post my results here when I am finished.

Sorry for the screw up.

Thanks,

John Pavan

Hi again,

I see that the adv_dbg_sys patch for or1200_du.v is not compatible with the or1200v3 RTL...which I believe is the base for orpsocv2 used in the Ubuntu image. (The patch failed badly for or1200v3...and worked perfectly for or1200v1.)

Here is a comment from the Known Bugs section of the OpenCores adv_dbg_sys project web page:

"The OR1200v1 hardware breakpoint implementation is broken. A patch which fixes the support is distributed with the Advanced Debug System in the Patches/OR1200v1/ directory. Support for other versions of the OR1200 is not yet available."

So it appears that I am in some trouble here. (It seems that I made some poor design selection decisions when assembling my system.)

I did verify that the HW breakpoints don't work with or1200v3 and the adv_dbg_sys using GDB on the bench.

Has anyone patched or1200_du.v in or1200v3 to fix the HW breakpoints problems?

I may try to fix it myself...but I am skeptical about my ability to succeed based on my current lack of knowledge about how the design works.

Thanks,

John Pavan

I made some design changes over the weekend to or1200_du.v in or1200v3. I based my changes on the changes that Yawn published in the patch file for or1200v1 that is distributed with the adv_dbg_sys project from OpenCores.

I think I have HW BPs working only for instruction addr break. (This is a feature my FW/SW folks requested for debugging with the Icache enabled.)

I've performed some initial verification on it in logic sim and on the bench running our custom firmware. I have not performed exhaustive verification yet.

I did not fix the other various issues with HW WPs that Yawn also addressed in his patch for or1200v1. I plan to work on that in the future. Those changes are a bit more significant and I needed to get basic HW BPs working now.

Hi,

I updated to the latest OR1200 RTL in SVN. The latest RTL seems to have several patches implemented in it.

I added a another patch to the RTL that I found on the OpenRisc email and forum threads.

I modified or1200_du.v to implement HW BPs in the manner Yawn did for the rel1 RTL. I've verified the changes in logic sim and tested the changes on the bench pretty well. (My system does not use the MMUs.)

I also modified rsp_server.c to work with the latest RTL and added copious debug printfs so that I could follow and track the RSP server call flow.

Merry Christmas,

pavan@surfnetusa.com