Please tell me if I understand a solution among FNolte, everybodies.
Use environment: Open RISC Actel ORDB1A3PE1500
�path : /ORPSoC/boards/actel/ordb1a3pe1500/sim/run
command: > make rtl-tests MGC_NO_VOPT=1

It becomes a result same as the contents which FNolte describes, and ModelSim "Error loading design "message appears, and the compilation result is finished before ModelSim start. (the following message)
It wants to be settled somehow.
�What kind of procedure did you solve this Error in; thanking you in advance?
(if this works well, I think that Actel development environment construction is the end)

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It is a problem at the time of publication before FNolte
Title:Open RISC Program memory
URL : https://opencores.org/forum,OpenRISC,0,5151

-------- Error Message Contents

### Compiling testbench ###

** Warning: /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../bench/verilog/include/eth_stim.v(126): Extra semicolon found. This is permitted in SystemVerilog, but not permitted in Verilog.
** Warning: /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../bench/verilog/include/eth_stim.v(127): Extra semicolon found. This is permitted in SystemVerilog, but not permitted in Verilog.
** Warning: /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../../../../bench/verilog/include/cfi_flash_TimingData.h(195): (vlog-2250) Function "getTime" has no return value assignment.

### Launching simulation ###

Reading /home/katsumi/ProgramFiles/Actel/Libero9.1/Model/modeltech/tcl/vsim/pref.tcl

# 6.6d

# vsim -do {set StdArithNoWarnings 1; run -all; exit} -c -quiet -suppress 8598 orpsoc_testbench
# // ModelSim ACTEL 6.6d Nov 2 2010 Linux 2.6.32-38-generic
# //
# // Copyright 1991-2010 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# ** Error: (vsim-3033) /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(262): Instantiation of 'GND' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(264): Instantiation of 'CLKDLY' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../../../../rtl/verilog/smii/smii_if.v(441): Instantiation of 'CLKDLY' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/smii0/smii_if0
# Searched libraries:
# /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/work
# ** Error: (vsim-3033) /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/../../rtl/verilog/sdc_controller/sd_clock_divider.v(16): Instantiation of 'CLKINT' failed. The design unit was not found.
# Region: /orpsoc_testbench/dut/sdc_controller_0/clock_divider_1
# Searched libraries:
# /home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/work
# Error loading design
Error loading design
make[1]: *** [modelsim] Error 12
make[1]: Leaving directory `/home/katsumi/data/org_orpsocv2/orpsocv2/boards/actel/ordb1a3pe1500/sim/run'