Hi all,
I am working on OR1200 processor. The cache of OR1200 has already been changed to 4- way set associative. Now I am trying to change the OR12000 Processor's External wishbone Interface to AXI. First I am trying to modify the BIU (bus interface unit) i.e without using the existing BIU I am generating AXI signals from cache(not modifying the cache) .


I would like to know If anyone else is working on OR1200 with AXI Interface.
Please let me know.


Thanks,
Karthik.