Hi, is there anyone had success implementing OpenRISC and orpsoc on DE2-70 board?
Is there any functional orpsoc port to de2 yet? If none, what should I do to orpsoc-cores to make de2 an available system on it?

Hi,

I don't think anyone has made a de2 port yet, but we are always interested in new ports, so we are here to help if you want to make one yourself. Your best option is probably to base it on the de1 port, as they seem to be most similar.

Make a copy of the de1 system and rename all de1 things to de2. After that you need to change the pin mapping (in data/pinmap.tcl), clock generation (backend/verilog/rtl/pll.v), configure the SDRAM interface for your board (wb_sdram_ctrl0 in rtl/verilog/orpsoc_top.v), add/remove peripheral controllers and regenerate wb_intercon.v

There are probably more things that need to be updated, but I hope that this can be helpful for getting started. We are also available at #openrisc on irc.freenode.net if you want to have a quicker conversation

Best Regards,
Olof Kindgren

I got a pull request for a de2 port earlier today (https://github.com/openrisc/orpsoc-cores/pull/38)

Was that you who made a port extremely fast, or was it just a lucky coincidence? :)