Hi All,

I have modified the Bus interface unit(BIU) of OR1200 processor(of ORPSOCV2) from wishbone to AXI , And I want to port it on FPGA, But I need a AXI Wrapper for the DDR2 controller so that processor can communicate with DDR2 in AXI. The present wrapper present in "opencores" is in wishbone.

Did anyone already worked on it and changed the Wishbone wrapper to AXI? If so, Can I have the modified Wrapper so that I can port my modified or1200 Processor on FPGA using the modified one.

Thanks,
Karthik.