



Description in Verilog source files
by blaha on Mar 30, 2014 |
blaha
Posts: 1 Joined: Mar 9, 2014 Last seen: Jul 20, 2014 |
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Hello
My name is Hynek Blaha, I'm 23 and I'm studying hardware at Czech Technical University at Prague. I have to learn how OpenRisc 1200 works for my for my work. I have already spent hours looking at verilog source codes, but it's hard to read it for me, because many signals aren't described (commented). I had read every documentation I found. Could you recommend me anything, where I might learn how OpenRisc architecture works in detail? I would really appreciate any documentation about OpenRisc CPU with schemas at register/signal level with comments if they exists. Thank you very much! Hynek |



