Hi,

I'm looking to get started with the OpenRISC but am unsure which of these two SoC designs I should use. What are the main differences between these projects? Specifically, I would like to know the following:

1. Do they use the same underlying OpenRISC 1200 code or are they different?
2. Is MinSoC based off of ORPSoCv2 or is it something else entirely?
3. Is MinSoC still being updated/maintained or is it now obsolete?
4. Is ORPSoCv3 currently working? I tried building the atlys design with Cygwin and it cannot find the .tcl file due to the /cygdrive/c path, but I don't know where to change things to fix it. I also don't know if ORPSoCv3 actually has software support yet or not, since there is very little documentation. What is the status on this?

Open ticket at https://github.com/olofk/fusesoc/issues
Don't forget to provide full error log.

Hi

They might use different snapshots, but or1200 core didn't change that much for some time, so it's not that important for the first step.

Yes and no.
Each soc comes in three parts:
1) Cores like or1200, uart16550, adv_dbg_if, jtag_tap that can be downloaded separately from opencores.org
2) Top module that interconnects cores from 1)
3) Build system of some level of ridiculousness.

Cores from 1) will be the same because they come from the same place. 2) is mostly similar for orpsocv2 and fusesoc. minsoc should have it differently.
And everyone invents its own 3). To tell you the secret, you can always get without it. Just download orpsocv2, add all *.v files in your Quartus or ISE, assign pins for the top module and, boom, you have the same result. But then you will need to understand what you are doing here, because there probably won't be any people on this forum willing to help you with your own setup.

Maybe.

Yes.

Define "software support".

Thanks indirasulo. I'm sorry I didn't respond sooner. I was expecting an email to tell me someone had commented on here but I never received one.

I found the solution to my problem with the atlys .tcl file for building as well. fusesoc was preparing all of the RTL source code files correctly, but it could not run atlys.tcl to run the ISE tools on it because the .tcl file had been created with Cygwin-style (/cygdrive/c) paths in it instead of the usual C:/ kind.

By replacing all of these paths with their C:/ equivalents in the atlys.tcl file and running the .tcl file using the Xilinx command line program xtclsh, I got a bitfile for ORPSoCv3 on the atlys board.

What I meant by "software support" was that I wasn't sure where to get the toolchain for compiling and debugging programs for ORPSoCv3. My guess is that I can just use the same one for or1200 or mor1kx and that should be fine. Thanks for your reply.

I see. This would require some small hack to get it work out of the box.

fusesoc dev seem to be tackling this problem: http://juliusbaxter.net/openrisc-irc/search?q=cygwin