Hi, I've been trying to get the OpenRISC 1200 processor running on the Virtex 6 FPGA and the board I have has its own host processor and also some APIs. Once the bitfile is loaded on the FPGA, you can run a C program on the host and use a FIFO-type of communication with the FPGA . In the examples given with the FPGA, we see the input sent through the FIFO "stream", is accepted on the FPGA and then it reads the output back once whatever logic has performed its duty and finally read back by the host (through the stream) and displayed.

So i thought maybe i could use some sort of memory (sorry for being vague, this is where i have issues) in place of the readmemh function used for simulation - this memory would be loaded into by me during runtime based on the program i want to run and then the processor begins to read from the memory and finally on completion it produces an output which i read out from the "stream".

I'd like to know if this can be done, or is my approach flawed? And either way, i'd appreciate some advice and direction

Thanks

Hi!

Your description is very general and it's not clear what problem are you trying to solve.
Maybe you need data2mem: http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/data2mem.pdf
It allows you to update memory initialization data in your .bit files.