Hi Julius,

I am working on Modifications of OR1200 Processor and I have generated a AXI Bus Interface unit for the or1200 Processor and I have also modified the Arbiters (Instruction and Data) to AXI but the problem that I have encountered is The Wrapper for DDR2 Controller that is existing is in Wishbone protocol , Can I have the access to the specifications sheet so that someone can re-write the Wrapper in AXI and it would be very useful contribution for those who are working on it.


Thanks,
Karthik.G