I use modelsim 10.1a to simulate the orpsoc system. During the simulation, i found that the value of some signals will be uncertainty. For example, the signal "lsu_dataout" in module or1200_lsu will be "000xx0000x00000000000000xxxxxxxx" at 640ns.
I want to know how it happens, and where the uncertain value comes from.

to do that, You have to check which logic block drives this signal. Then check all the inputs to this block to find which one has undefined values. Then do it again for this input signal. This way You will find the chain of blocks that propagate the undefined value. At the begening of this chan You should find some driver signal from the testbench or maybe a register that wasn't reset at the begining of the simulation.

Hi,

in fact that is nothing bad. It becomes a bug if this data is important in this cycle. In other cases it is just undefined. It can then be used for optimization ("don't care", remember).

So, is your question just for curiosity or do you think there is a bug?

See you,
Stefan

Thanks Stefan. I need the value of the signal to be definite, just 0 or 1, during the simulation. So, I want to trace back the uncertainty signal, then find the source of "X". Then, initial the source signal to be definite. Thus, my question is what is the source: dpram/spram/fifo or other modules �(���)�