Hi, All:
I got a question when studying openrisc core. That is openrisc 1000 is a full instruction set, while current openrisc cores (for example, or1200, mor1kx, altor32 and etc) are only implementes the subset of it, which means not all insturction could be excuted on these openrisc cores. In or1200 IP core specification, I could find the table 3.1 for instructions implemented in or1200.
My question is that whether there are different inscturcitons implementation between these openrisc cores(or1200, mor1kx, altor32 and etc)? Which means if I compile the machine code for mor1kx using "or1k-elf-gcc", can I use it for or1200 directly (suppose the hardware configuration is the same)? If not, how can I set the opencore type when compiling c/assembly program?

Thanks!

lemonsky

Hi lemonsky,

Short answer is: Yes and no :)

Long answer: This should work in most cases. All of the CPUs listed implement the ORBIS32 instructions, which is the basic 32 bit instruction set. Some instructions (l.mul, l.div and a few more) can be optionally omitted, but I guess all the cores have parameters for enabling or disabling them, so with a similar hw configuration you should be fine.

Another thing is the FPU. Up until recently, mor1kx didn't have an FPU, so floating point instructions would not work there. On the other hand, I think you can set a flag to the compiler to build with emulated floating point instructions, so that should take care of that issue.

Another thing is the atomic operation support (l.lwa/l.swa) that was added quite recently to the spec. These instructions are mainly for synchronising multiple cores/threads, and is only implemented in mor1kx as far as I know. I think that atomic operations are currently only used in Linux and since you are talking about the or1k-elf toolchain, I assume you are using it for bare-metal programs, so this shouldn't be a problem here either.

The last thing that comes to mind is implementation bugs. I think there might be a few workarounds at least in the kernel for some bugs specific to a certain implementation, but this is true for all processors I guess, so it's nothing OpenRISC specific.

Good luck

olof, thanks a lot for your reply!