I get an illegal instruction exception.
As far as I can see it has nothing to do with the Verilog or the simulation
or the target settings.
The core throws a tantrum when it reads in the instruction "0xb8630002"
Tracing where that comes from the disassembly produces this:
...
102f8: 84 62 ff f8 l.lwz r3,-8(r2)
102fc: b8 63 00 02 l.slli r3,r3,0x2 10300: e0 64 18 00 l.add r3,r4,r3
...
Looking at the instruction set I get a problem because the
open risc architecture document says that l.slli has opcode 0x2E.
The webpage differs: https://sourceware.org/cgen/gen-doc/openrisc-insn.html#insn-l-slli
That shows 0x2D as opcode..
But neither of them are 0xb8 so the Verilog tantrum seems to be correct.

I know most about hardware so I had one of our SW gurus install the tools for me.
I run gcc with --version and it tell me it is 4.9.1

The lli instruction is used regularly (and is wrong everywhere
in my disassembly) so this must have tripped up others.
Which make me believe I did something wrong.

Do I have the wrong tools set?
Do I have the wrong Verilog version of the or1200?

Help appreciated.

Hi,

There is nothing wrong with the instruction itself. The opcode field is six bits so you have to ignore the two lowest bits in the byte, i.e. b8 = 101110(00), 2E=101110. Don't know why the cgen doc page says 2d, but looking at the actual CGEN code, the correct value is definitely 2E

I can't offer any explanation for why you're getting an illegal instruction error however. You might have a bad version of or1200, but it's hard to tell without knowing where you got it :)

Out of curiousity, have you considered using mor1kx instead of or1200? That's where we are focusing our development nowadays, so you will most likely find better support there, as well as quicker bug fixes. It's also both smaller and faster than or1200

Best Regards,
Olof

Olof,
thank you for the information.
I chose the or12K because I thought it was the latest up-to-date revision.
I just spend two hours removing the or1200 and replacing it with the mor1k.
(And recompiling the boot-rom and main program code etc. etc.)
I also had to fix a compiler error in the mor1kx_lsu_cappuccino.v
(Line 249 has to be moved down as it is using variables and localparams which have not yet been defined).
As in the or1200 I had to clear the register file memories using an 'initial' statement to clear register 0.
The effort seems to have paid off as the illegal instruction has gone.
I have now "Hello world!" coming out of my UART (in simulation)

Again: thnk you it all seems to work.

p.s. if my boss allows I might throw some of my files to you.
I have fixed the wishbone to AHB converter and have a basic bootrom.

Hi,

Happy to hear that it's working now.

As a matter of fact, I submitted this patch https://github.com/openrisc/mor1kx/pull/24 recently to mor1kx to allow clearing RF in simulations. I also have the same patch to move around the localparam (modelsim complaining, right?) but have forgot to send that one in. So you're not alone having those problems :)

Regarding the bootrom, I have been working on one as well, that loads verilog $readmemh files to initialize the ROM. It's not available yet but my small (hopefully growing) collection of bootloaders to put into the ROM can be found here https://github.com/olofk/or1k_bootloaders if you are interested.

Hope your boss allows you to share some files. I know that people have been interested in the AHB bridge, and giving as well as taking is what keeps this community alive.

Feel free to join us on IRC (#openrisc on irc.freenode.net) as well if you want to get in quick contact with the main OpenRISC developers

Cheers,
Olof