Hello everybody,

In first, sorry for my English.

I try/learn to use the openRISC processor.
I have the de0-nano for play.
I just instanced the processor mor1kx in pronto espresso (de0_nano.vhd).
One the data wishbone interface, I just indicate 0x87654321 value (why not).
One the instruction wishbone interface I connected a small memory for test some instruction (mempgm.vhd).
I give you my project (or1k.zip) with this files if you want see.

Below, my memory with the simple test instructions.
signal mem : memory :=(
x"15000001", --l.nop 1
x"15000002", --l.nop 2
x"15000003", --l.nop 3
x"15000004", --l.nop 4
x"15000005", --l.nop 5
x"15000006", --l.nop 6
x"15000007", --l.nop 7
x"18000000", --l.movhi r0,0x0
x"18200000", --l.movhi r1,0x0
x"8421000c", --l.lwz r1,12(r1)
x"d4000804", --l.sw 4(r0),r1
x"1500000c", --l.nop c
x"1500000d", --l.nop d
x"1500000e", --l.nop e
x"1500000f", --l.nop f
x"03fffff1" --l.j -15
);

The file stp1.png and stp1.vcd (gtkwave can open this format) is the acquisition after reset signal.
So, you can see, the instruction run correctly, buy I don't understand why, the address is not incremented on the all rising edge clock but all the two rising edge.
I read somewhere, openRISC that take two clock cycle to access the memory. It is possible to change this parameter (to put less or more) ?

I don't understand the cti signal on wishbone interface where a can get the information ?

Thanks in advance,
Antoine

Hi Antoine!

You can find the specs for the wishbone interface here:

http://cdn.opencores.org/downloads/wbspec_b4.pdf

As I understand the interface, the CYC line needs to go down between each bus access. This forces you into a two clock access. To go faster, you need to try some of the pipeline or burst mode options associated with the interface.

Dan