I am trying to understand the memory hierarchy of openrisc.

As described in the file or1200_top.v, instruction cache and data cache are not connected directly to cpu. They are connected to a memory mamed QMEM, which is then connected to IMMU and DMMU. Only IMMU and DMMU are directly connected to cpu.

But this is contradicted by some comments made by damjan lampert:
ftp://134.76.12.4/pub/misc/opencores/ml-archive/archives/openrisc/0307/msg00039.html

If I understood him correctly, he claims that qmem and IC/DC caches are completely independent, which (in my opinion) is contradicted by the layout described in top.v

Also, in the following layout, it is suggested that the cpu can access IC/DC caches directly (and hence independently of QMEM).
http://www.tessera.co.jp/opencores/or1200_block.pdf
This also contradicts to what I understand from the code.

Cam somebody describe the memory hierarchy or or1200 in plain terms? How are IC/DC, IMMU/DMMU and QMEM connected? Can I design a system without QMEM?