Hello,

im a master student in germany and im working on a project for my university.
We are trying to implement an CPU on a FPGA (Altera Cyclon IV) to build a so called "MIDI Router".
Therefore i want to use the minsoc project and add as many modules as possible.
I've no problems with compiling the minsoc project in Quartus II but i was looking for some solutions how to
add modules to the system.

To add moduels to the system i have to expand these files?

- "minsoc_top.v" (Top-Level-Design to add module instances)
- "minsoc_tc_top" (interconnection slots)
- "interconnection_devices.v" (address ranges)

1.) So how many modules can be add to the wishbone bus?
- Because we need as many I/Os (GPIOs and UARTs) to route MIDI-Signals.
- So for example several instances of the UART and GPIO modules.

2.) Is it possible to resize the wishbone bus and add more target slots?
- minsoc.pdf rev1.1 (2.2.1)
- free targets for example are (t4_addr, t6_addr, t7_addr, t8_addr) is that correct?
- To attach a new module to the system, the file �minsoc_top.v� has to be edited
and interconnect slots must be available.

I hope you can help me.

Best regards

Hi,

Have you looked at using FuseSoC (https://github.com/olofk/fusesoc), and extending one of the systems in orpsoc-cores (https://github.com/openrisc/orpsoc-cores/tree/master/systems) instead of using minsoc? There are several Altera-based systems there already. Especially the de0 nano port, which also uses a Cyclone IV and is used quite a lot

//Olof

Hi Olof,

thanks for your reply. Fusesoc is a very good alternativ.

But could you maybe explain me how to extend such a system? Or should i build a system for my own?

- creating system interconnections with the interconnect generator or adding modules by extend these files
(for example: wb_intercon.v, wb_intercon.vh, orpsoc_top.v)

- module addresses are defined in wb_intercon.v right?

- Or is the top-level file created by fusesoc?

regards

Hello Bastian,

for an overview, have a look at doc/minsoc.pdf Section 2.2 Wishbone Interconnect.



You only have to change minsoc_top.v. You can change interconnect_defines.v to change the definition names if you like. But that is not necessary for a functional module connection.



You can add a total of 9 modules. But you need memory for code and variables, thus 8 remain. Check the table at the page 11 of doc/minsoc.pdf.



Not with MinSoC. You can add as many modules as you wish with Fusesoc. I will answer your question about Fusesoc in another reply.

Best,
Raul

Hello again Bastian,



That is right.



No and no.



If you want to extend the system, pick something under orpsoc-cores/systems, de0_nano for instance, and adapt it. What interests you most is probably data/wb_intercon.conf. In this file, all module connection can be configured. You start with a master and define its slaves. For which named slave, you define its offset and size for the address space of that master. If the slave has an 8-bit data width Wishbone connection, define data width=8. If the module works with 32-bit Wishbone, no definition is necessary.

When you're ready, run ../../../cores/wb_intercon/sw/wb_intercon_gen my_intercon.v my_intercon
Files my_intercon.v and my_intercon.vh will be generated.

The regular system uses the module's name wb_intercon and the files wb_intercon.v and wb_intercon.vh under rtl/verilog. If you look into orpsoc.v, you will see that at line 154 and 155, both files are included. The wb_intercon.vh is a helper file with all required wire initialisations and also the instantiation of the interconnect module itself. At line 260, or1200_top is instantiated and connected to this interconnect, it uses the wires wb_(m2s|s2m)_or1k_i_***. m2s means master to slave and s2m means slave to master. Lines 493 to 506 are an example for a slave connection. The *** stands for the slave or master name at wb_intercon.conf file.

I hope that helps too, let us know how you're doing as you go along.

Best regards,
Raul