Hi, everyone.

Does anyone has the experience for accessing SRAM with debug proxy interface through wishbone bus?
I'm now working on a project of a chip of or1000 core with the SRAM we made and the GNU debugger interface.
The debugging physical target block diagram as in the following link:
http://opencores.org/or1k/Debugging_physical_targets_(FPGA/ASIC)#Run_the_UART_terminal

The chip is already taped-out and we wish to test the function of the SRAM. However, the bootloader of SRAM doesn't work and we have no extra test pins on the chip, the only way we can access and test our memory seems to be GNU debugger interface. I'm now trying to write/read data to the memory through using usb functions of the GNU debugger through the wishbone bus, is there a suitable way to achieve this?