i solved previous problem for remove some module.

and i have two questions.

as far as i know, JTAG tap is connected to PMOD connector.

so, how can i upload elf file to atlys board and using PMOD connector?

An error occurs when i try to connect a usb-jtag of atlys board in ubuntu.

USB device 'Digilent Development board JTAG' with UUID {bedb2fce-84c2-41da-970b-e3a700f0f3d4} is busy with a previous request. Please try again later.

how can i solve this problem?

If you are using the ATLYS board described here, then there is no JTAG connection to any PMOD ports. JTAG is available either through the USB port, or through a 2x7 programming header labeled J10.

Hope this helps,

Dan

according to atlys.ucf file in fusesoc, jtag_tap module(in fusesoc) is connected pmod connector.
so, i want to know how can i use pmod connector

Okay, ... I got some helf from Olof.

The PMOD connector on the Atlys does not connect to the JTAG FPGA port. In connects instead to a soft JTAG" port that is instantiated in FPGA logic. This soft port can be used by a JTAG controller to access and configure a CPU within the FPGA, such as OpenRISC.

The recommended driver for using this jtag_tap port is the OpenOCD driver.

Dan

Can i use JTAG_TAP module by JTAG port.

do i use JTAG port to anyport(in atlys board) for connect JTAG_tap module to OpenOCD

i don't know what port i use for connect JTAG_tap module to OpenOCD

I don't know correctly wrote the because my English skills is not good

i want to use fusesoc on atlys in two of the conditions.
i use two JTAG

first JTAG is atlys board's JTAG port(J17 or J10)

second JTAG is connect to fusesoc(i think i use PMOD connector)

i want to connect openOCD and PMOD connecter(second JTAG)

do i have to use special JTAG when using the second JTAG(PMOD connector)?

or which of the cfg file in openOCD do i use

Hi,

Sorry for the long delay. I've been very busy lately. I think there are two options, but both might be a bit tricky.

It turns out that you can use the internal FPGA JTAG connector, which is the one that is connected to the Xilinx 2x7 pin header and the uUSB connector. This is the one used for loading the FPGA. To do this however you would need to instantiate the xilinx bscan primitive and connect to adv_debug_sys in the FPGA source code. You would also need to reflash the FX2 chip which is responsible for translating the USB commands to JTAG. I can't give you further directions on this as I don't own an atlys board anymore, and haven't tried this option myself. If you are on IRC however, please come to the #openrisc channel on irc.freenode.net, because there are people in there who knows more about this than I do.

The other option is to use jtag_tap via the PMOD connector, and this is the option that is currently set up for the FuseSoC atlys system. This however requires you to use an external JTAG adapter, and connect the pins on that to the correct pins on the PMOD header. Unfortunately, I don't own any external JTAG adapter either, and don't know enough to recommend one.

A third option, which I know people are doing, is to store a boot loader to the on-board SPI Flash on the Atlys such as U-boot and set up the system to always read that upon startup. Once u-boot is started, you can then load another program via ethernet. Again, I would recommend to join us at IRC to find out people who know more about the exact details than I do.

Hope this helps,
Olof