I use the fpu from OpenRISC(mor1kx implementation). I would be grateful if anyone told me the usage of padv_decode_i and padv_execute_i inputs signals. I know that they are pipeline control signals but I can't understand how they are used. For example when they asserted zero or one and how the fpu communicate with the whole microprocessor with these signals?

Short answer: FPU communicates with CAPPUCCINO pipe in the same way as serial divisor.

Some details.
  In general the CTRL stage (mor1kx_ctrl_cappuccino.v as we are speaking about CAPPUCCINO pipeline) collects "valid" / "busy" signals from all pipe stages, analyses them to understand pipe status and generates padv_* control signals. If EXECUTE stage executes a multi-cycle instruction (like division) the DECODE and EXECUTE stages are stalled till the instruction completion. All of FPU instructions are multi-cycle. Even so CAPPUCCINO's FPU is internally pipelined it integrated with other CPU in the same way as serial divisior. That means the pipeline is stalled till FPU instruction completion. The reason is it was the straight way to integrate multi-stage FPU pipes with classic 6-stage pipeline taking into account that OR1K uses same general propose registers for integer and floating point instructions.
  There is MAROCCHINO pipeline (github.com/openrisc/mor1kx/tree/marocchino_devel). It implements Tomasulo algorithm and provides better performance especially for multi-cycle instructions like FP- ones. It also supports single and double precision FP- arithmetic. The double precision FP- instructions are implemented in according with (openrisc.io/proposals/orfpx64a32) proposal. The pipe control is quite similar to CAPPUCINO's one: "valid" signals from various pipeline stages are collected in CTRL module (mor1kx_ctrl_marocchino.v) to compute padv_*. However, order control buffer are added to grant WB-common bus access among parallel execution pipes and provide in-order write back.
  If you need more details, I think you have to go through source code and study it by yourself. Pay attention how various "valid" and "busy" flags are generated in integer/FP parts and propagate through integer/FPU stages.