![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)
Wishbone interface in OR1200
by OmarAlaa148 on Jun 11, 2017 |
OmarAlaa148
Posts: 1 Joined: Aug 2, 2016 Last seen: Apr 3, 2020 |
||
Hello all,
I'm new to using the OR1200 processor. I downloaded OR1200 uder URL: https://github.com/openrisc/or1200 I'm trying to simulate the OR1200_top module using the instruction WISHBONE interface. I just want to execute "l.mtspr" instruction to go to user mode and then execute another instruction found in the ISA of OR1200. I'm facing hard time loading these instructions through the WISHBONE interface in RTL. I'm using Xilinx ISE for RTL simulation. Here is a part of my testbench: ------------------------------------------ -- Stimulus process (clock period =5 ns) stim_proc: process begin clmode_i iwb_err_i iwb_rty_i rst_i iwb_rst_i wait for 5 ns; rst_i iwb_rst_i iwb_dat_i wait for 5 ns; iwb_ack_i wait for 5 ns; iwb_ack_i iwb_dat_i wait for 5 ns; iwb_ack_i wait; end process; ------------------------------------------- What is my mistake ? Any help would be appreciated. Thanks |
![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)