hi,
I'am new to openrisc
Now, I have finished the ORPSoC system on
de0_nano starter kit
adv_jtag_bridge works well when jtag_tap is ALTERA_JTAG_TAP
but the ORPSoC system has problems when jtag_tap is GENERIC_JTAG_TAP.
the log:


The GENERIC_JTAG_TAP self-test report is as follows，it is the same as using the ALTERA_JTAG_TAP test result.
____________________________________________________________________________________
openrisc@openrisc-VirtualBox:~$ adv_jtag_bridge -t vpi
Enumerating JTAG chain...

Devices on JTAG chain:
Index Name ID Code IR Length
----------------------------------------------------------------
0: OC_TAP 0x14951185 4

Target device 0, JTAG ID = 0x14951185
IDCODE sanity test passed, chain OK!
*** Doing self-test ***
Stall or1k - CPU(s) stalled.
SRAM test:
expected 11112222, read 11112222
expected 33334444, read 33334444
expected 55556666, read 55556666
expected 77778888, read 77778888
expected 9999aaaa, read 9999aaaa
expected bbbbcccc, read bbbbcccc
expected ddddeeee, read ddddeeee
expected ffff0000, read ffff0000
expected dedababa, read dedababa
SRAM test passed
Testing CPU0 (or1k) - writing instructions
Setting up CPU0
Starting CPU0!
Read npc = 00000010 ppc = 00000028 r1 = 00000005
Expected npc = 00000010 ppc = 00000028 r1 = 00000005
Read npc = 00000028 ppc = 00000024 r1 = 00000008
Expected npc = 00000010 ppc = 00000028 r1 = 00000008
Read npc = 00000024 ppc = 00000020 r1 = 0000000b
Expected npc = 00000028 ppc = 00000024 r1 = 0000000b
Read npc = 00000024 ppc = 00000028 r1 = 0000000b
Expected npc = 00000024 ppc = 00000020 r1 = 00000018
Read npc = 00000024 ppc = 00000020 r1 = 0000000b
Expected npc = 00000020 ppc = 0000001c r1 = 00000031
Read npc = 00000020 ppc = 0000001c r1 = 0000000c
Expected npc = 00000024 ppc = 00000020 r1 = 00000032
Read npc = 00000020 ppc = 00000024 r1 = 0000000c
Expected npc = 00000014 ppc = 00000010 r1 = 00000063
Read npc = 00000020 ppc = 00000024 r1 = 0000000c
Expected npc = 00000028 ppc = 00000024 r1 = 00000065
Read npc = 00000010 ppc = 00000028 r1 = 00000016
Expected npc = 00000010 ppc = 00000028 r1 = 000000c9
result = deadd85d
Self-test FAILED *** Bailing out!

________________________adv_jtag_bridege shown_______________________________

openrisc@openrisc-VirtualBox:~$ adv_jtag_bridge vpi
Enumerating JTAG chain...

Devices on JTAG chain:
Index Name ID Code IR Length
----------------------------------------------------------------
0: OC_TAP 0x14951185 4

Target device 0, JTAG ID = 0x14951185
IDCODE sanity test passed, chain OK!
No watchpoint hardware found, HWP server not starting
JTAG bridge ready!
CRC ERROR! Computed 0x25ea92fb, read CRC 0xffffffff
Retry count exceeded! Abort!

Error while reading all registers: 'CRC mismatch'


___________________GDB(or32-elf-gdb) shown_________________________________
openrisc@openrisc-VirtualBox:~$ or32-elf-gdb
Building automata... done, num uncovered: 0/216.
Parsing operands data... done.
GNU gdb (OpenRISC 32-bit toolchain for or32-elf (built 20111014)) 7.2-or32-1.0rc3
Copyright (C) 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later " target="_blank">http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=or32-elf".
For bug reporting instructions, please see:
." target="_blank">http://www.opencores.org/>.
(gdb) target remote :9999
Remote debugging using :9999
Remote failure reply: E01

I have tried the following method：
1. adv_jtag_bridge, open rsp-server.c in a text editor and change the GDB_BUF_MAX back to its earlier value of ((NUM_REGS) * 8 + 1).
2. Try disabling the JSP feature in adv_jtag_bridge.
3. test the value of your CLOCK_DIVISOR and check that the CPU is getting a reset pulse of sufficient duration