Hello All,

I have completed my Bachelor's in Electronics Engineering and have completed an industrial training in Advanced RTL Design and Verification.

I have good exposure to design and verification domain with the following qualifications:
* Good understanding of the ASIC and FPGA design flow
* Extensive experience in writing RTL models using Verilog HDL.
* Good experience in writing Testbenches using SystemVerilog and UVM
* Very good knowledge in verification methodologies
* Experience in using industry standard EDA tools for the front-end design and verification.

I am attaching here my Resume for further details about my skills and projects. I request you all to kindly give me an opportunity to contribute to your project. I would be very thankful and happy.

Regards,
Tasmai Joshi

Dear Sir,

Would you please stop spamming projects with your request to join.

I have seen it now many times. It is sent to every member who has an active account here. Even if we are not maintaining projects.

I am fairly sure that every active member has seen your request.

Thank you, for your attention.

metaforest is absolutely right. TDJ please avoid posting the same request/comments on multiple forums.
We deleted a few now, please think before acting.
Thank you for the cooperation.
Best,
/:/ OC-team

Hi,

I am sorry for spamming. I did not know that if I post it on one forum, it will be visible to all other forums.

My mistake. Sorry

Regards

Thank you for your attention.