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Wishbone Verification Project
by ruschi on Jul 2, 2009 |
ruschi
Posts: 4 Joined: Mar 15, 2009 Last seen: Oct 11, 2017 |
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Hi fellow members,
personally I have no experience in professional hardware verification with frameworks like OVM etc. However it came to my mind that it would be quite useful to launch a project (if it doesn't already exits) that comes up with some kind of generic wishbone master / slave interface which can be used for verifying other cores for whishbone compliancy. I know comparable things exist for field bus devices and I think ARM also has something to test AMBA compliancy. What do you think - and if you think its good. will you join me in the effort of creating such a piece of software/HDL testbench? do you think it is actually necessary, somehow I have my doubts.... --- Cheers ruschi |
RE: Wishbone Verification Project
by madengineer on Jul 3, 2009 |
madengineer
Posts: 2 Joined: Jun 3, 2008 Last seen: Nov 8, 2010 |
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Hi Ruschi,
I think you're right - such a tool would be useful. I've killed a Wishbone bus based system before by introducing (my own) non compliant buggy module onto the bus... It would be helpful to have a standard way of checking compatability, instead of every Wishbone module developer creating their own testbenches to do this. Have you had any other interest? Best regards, Richard. |
RE: Wishbone Verification Project
by vancejs on Feb 8, 2010 |
vancejs
Posts: 2 Joined: Aug 3, 2009 Last seen: Mar 10, 2010 |
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This is a slightly old thread, but I just noticed it and wanted to reply.
I might be interested in working on such a project. Although I haven't been involved in any OpenCores projects in the past and am not incredibly familiar with the wishbone spec (not yet), I have some experience doing verification. I'm actually looking for opportunities to get more experience with verification and this sort of project would be perfect. Although I've used OVM and SystemVerilog in the past, I'd imagine to be more useful for open source projects it makes more sense to stick with Verilog and maybe use OVL for assertions. OVM is really great, but I don't believe there are any open source tools that support SystemVerilog yet (unfortunately). |
RE: Wishbone Verification Project
by syswip on Feb 12, 2010 |
syswip
Posts: 1 Joined: Nov 10, 2009 Last seen: Jul 20, 2017 |
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Hi folk,
I have free SystemVerilog Verification IP for Wishbone bus. You can download it from my site http://syswip.com/wishbone-verification-ip I think it will help you to create your Wishbone verification environment. Bests, Tiksan http://syswip.com |
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