OpenCores
no use no use 1/1 no use no use
UART 16550
by aksarup on Jul 28, 2009
aksarup
Posts: 1
Joined: Jul 27, 2009
Last seen: Sep 12, 2019
Hi I have just download the uart16550 and tried to run it using modelsim.
But unfortunately I wasn't successful, to begin with the script was looking for the tests in bench/verilog/testcases where as the dir there is bench/verilog/test_cases.
Have edited the script I ran again but now I get some messages -
# *E, Bit 5 of LSR register should not change!
# *E, Bit 6 of LSR register should not change!

And the test just finishes putting in some debug messages it looks like some err_event is triggered and the test bails out.

Has anyone had any success with the so far or is it too old a thing to be bothered with.

Thanks
Akshay Sarup
RE: UART 16550
by sckoarn on Aug 20, 2009
sckoarn
Posts: 3
Joined: Feb 1, 2007
Last seen: May 7, 2024
We are using this UART where I work.
I tested it, not using any supplied test environment. It does not function like it is documented. Our Software group is using it and have found that it does not function like it stated in the doc. We are able to make a serial communication link work regardless.

I would only use the DUT source and your own test environment.

Sckoarn ;(
RE: UART 16550
by jeremybennett on Aug 20, 2009
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

There are several UART projects on OpenCores. Which one are you using? Not all of them claim to be complete.

You could try raising a bug in the projects bugtracker. I notice the VHDL UART16550 project seems to be complete and active, with the most recent bug fixed a in June this year.

HTH

Jeremy

--
Tel: +44 (1590) 610184
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com

RE: UART 16550
by dragon_vnu on Feb 3, 2012
dragon_vnu
Posts: 1
Joined: Dec 6, 2010
Last seen: May 18, 2012
I have the embedded system which used the wb_uart16550 IP core.
But when I implement it on my system, I met an error that:
" ERROR:HDLCompilers:26 -
"D:\5.Project\pcores\wb_uart16550_v1_00_a\hdl\verilog\uart_sync_flops.v" line

71 Could not find verilog include file 'timescale.v'
"

Anyone can help me to solve this problem
Thank !

--
==================================
Quoc Long - Bui

K53� - Faculty of Electronics and Telecommunications,
University of Engineering and Technology (UET),
Vietnam National University, Hanoi (VNU)
Tel : (+84) 988 652844
Email : dragonvnu@gmail.com
==================================
no use no use 1/1 no use no use
© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.