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Wishbone Verilog API
by farhan83 on Aug 8, 2009 |
farhan83
Posts: 1 Joined: Jul 31, 2009 Last seen: Oct 10, 2009 |
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hi everyone,
i'm looking for Wishbone verilog API. i didnt find the link in this website to the wishbone API. i'm working on NoC now, and would like to interface my network adapter to core using wishbone interface. Please help. Thanks regards, Farhan |
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RE: Wishbone Verilog API
by jeremybennett on Aug 9, 2009 |
jeremybennett
Posts: 815 Joined: May 29, 2008 Last seen: Jun 13, 2019 |
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i'm looking for Wishbone verilog API. i didnt find the link in this website to the wishbone API. i'm working on NoC now, and would like to interface my network adapter to core using wishbone interface.
Hi Farhan, Do you have all the information from the Wisbhone project page: www.opencores.org/?do=wishbone? This has the full bus specification. The specification is independent of any particular implementation. I don't believe there is a Verilog reference implementation of the API. However you could look at ORPSoCv2 (http://www.opencores.org/openrisc/?orpsocv2), for examples of both master and slave implementations. I believe Richard Herveille (the originator of WishBone) is still involved with OpenCores. He may be able to point you to a particularly good implementation in Verilog. HTH Jeremy
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