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[vhdl] user-defined attributes
by deltadelay on Sep 10, 2009 |
deltadelay
Posts: 1 Joined: Jul 24, 2009 Last seen: Feb 6, 2017 |
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Hi to all!,
I should define a new type in order to manage the floating point format (32 bit, single precision). I could define a subtype as follow:
subtype fp_ieee754 is std_logic_vector(31 downto 0);
I would define some attributes, for example: width should return the length of this subtype, sign should return the bit at position 31, exponent should >return the std_logic_vector(30 downto 23), etc....
So I could define a new signal of type fp_ieee754 and use its attributes, for example:
signal number : fp_ieee754 :=
if number'sign = '0' then
...
else
...
end if;
Is it possible?
Thanks a lot!
Vincenzo
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RE: [vhdl] user-defined attributes
by eilert on Oct 8, 2009 |
eilert
Posts: 1 Joined: Jun 26, 2008 Last seen: Jul 9, 2024 |
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Hi,
This is a very special question. You should post it on comp.lang.vhdl The guys there probably know the answer. Have a nice synthesis Eilert |
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