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models for AXI, DDR2
by anish on Nov 18, 2009 |
anish
Posts: 1 Joined: May 4, 2009 Last seen: Nov 18, 2009 |
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Hi,
I am doing some analysis for which I require models of DDR2 memory and AXI bus. Do open-source models for DDR2 and AXI exist. I am doing most of my development in myhdl-python, so it would save me a lot of time if such models already exist. Thanks, Anish |
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RE: models for AXI, DDR2
by jeremybennett on Nov 18, 2009 |
jeremybennett
Posts: 815 Joined: May 29, 2008 Last seen: Jun 13, 2019 |
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Hi,
I am doing some analysis for which I require models of DDR2 memory and AXI bus. Do open-source models for DDR2 and AXI exist. I am doing most of my development in myhdl-python, so it would save me a lot of time if such models already exist. Thanks, Anish Hi Anish Manufacturers of DDR2 memory often provide Verilog models of their IP for simulation purposes. These are not strictly open source (there are restrictions on how you use them, modify them and redistribute them), but they may be appropriate for your purposes. There has always been a problem with AMBA bus models. Although the standards are public, ARM keeps very tight rein on them, so developers have been nervous about writing open source implementations. I've always been frustrated by the lack even of good general AHB models. I'm not aware of any AXI models at all - if you find any let us all know. Jeremy
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RE: models for AXI, DDR2
by sekhar29 on Jun 22, 2011 |
sekhar29
Posts: 1 Joined: Jun 11, 2011 Last seen: Jul 26, 2011 |
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hii ..
i am sekhar.. i am developing AXI COMPLIANT DDR3 CONTROLLER.. so, i need some help regarding this project .. i am developing in verilog... if you had any files plzz send to me |
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RE: models for AXI, DDR2
by jay2524 on Jan 6, 2012 |
jay2524
Posts: 1 Joined: Jan 6, 2012 Last seen: Apr 18, 2012 |
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hi, i am working on AMBA AHB compliant memory controller. if anybody has files related to this plz send me..
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