Hi everyone,

I would like to know where it's possible to get VHDL to Verilog code converters?
Any kind of help is appreciated.

You could use VASY from alliance tools, specify the output format to verilog output with command option -v.

Hi f34rbod,

There have been a number of commercial attempts in the last decade, but none of them have been successful. They often work for small examples, but fail for large complex designs. There are a number of reasons for this:

1. Verilog and VHDL both have complex, and in many cases poorly defined IEEE specifications. Ambiguities in the Verilog IEEE standard must be resolved by seeing how Verilog XL behaves. That is not a good basis on which to make a machine translation.

2. Verilog and VHDL have different simulation semantics. It is extraordinarily hard to reconcile these, so simulations (and hence regression tests) are not consistent.

3. VHDL is a bigger and more complex language than Verilog, so some constructs (for example assertions) do not have a true equivalent.

In practice this ceased to be a commercially worthwhile exercise once all the mainstream tools supported mixed Verilog and VHDL.

You will note that in the past IP providers like ARM provided all their IP in both Verilog and VHDL versions. Now they only provide a single language version, relying on tools to handle any language mixing required.

However this remains a problem for the open source community, since the existing tools (GHDL, Icarus Verilog, Verilator) are currently single language.

Daryl Stewart at the University of Cambridge (now at ARM) wrote his PhD dissertation on the formal semantics of Verilog and VHDL. I can't find it online, but you should be able to gain access to it through any University library. You may also like to look at Cambridge University Computer Laboratory Technical Report 485, Three notes on the interpretation of Verilog by Daryl Stewart and Myra Van Inwegen.

Sorry this doesn't give you a solution, but I hope it is useful background.

Jeremy

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I have discovered that there is an archive copy of Daryl Stewart's work and the paper with Myra Van Inwegen online:

web.archive.org/web/20031224210630/www.cl.cam.ac.uk/users/djs1002/

I understand this copy of the thesis is prior to its final corrections, so treat with the appropriate caution.

Jeremy

@arif_endro---thanks for the info. i will surely try it out


@jeremy---Now thats a very good insight into it. I appreciate your time and help.

Thank you both of u :)

Hi,

I'm looking for translator from VHDL to Verilog.
I have a code written in VHDL and I need to translate it to Verilog.
Maybe you used one?
Please, any help is good help.

Thanx

There is no approach except for how to learn VHDL. But when you will learn you can write in both languages using their strengths.

If the attached code is the code you are looking to convert, then the only help I can offer you is to suggest that you just translate it by hand... The process should take about an hour, worst case...

Hii everyone.
I want description and verilog code of IWLS'05 benchmark circuit.Please someone tell me.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity Top is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0);
MemOE : out STD_LOGIC;
MemWR : out STD_LOGIC;
FlashCS : out STD_LOGIC;
FlashRP : out STD_LOGIC;
MemAdr : out STD_LOGIC_VECTOR(26 downto 1);
MemDB : inout STD_LOGIC_VECTOR(15 downto 0)
);
end Top;

architecture Behavioral of Top is
signal slow_clock : STD_LOGIC;
signal led_reg : STD_LOGIC_VECTOR(7 downto 0);
signal state : unsigned(3 downto 0) := "0000";
signal state_next : unsigned(3 downto 0);
begin

led
-- Clock Generation
clock_core : entity work.ClockCore
PORT MAP
(
clock => clock,
clock_3375 => slow_clock, -- 3.375 Mhz clock
RESET => reset
);

process (slow_clock, reset)
begin
if (reset='1') then
state led_reg elsif (slow_clock'event and slow_clock='1') then
state if (state = "1110") then
led_reg end if;
end if;
end process;

MemAdr MemDB MemWR FlashRP
process (state)
begin
case state is
when "0000" =>
-- initialize
FlashCS MemOE when "0001" =>
-- enable flash
FlashCS MemOE when "0010" =>
-- enable flash output
FlashCS MemOE when others =>
-- hold steady
FlashCS MemOE end case;
end process;

state_next
end Behavioral;