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VHDL to Verilog
by f34rbod on Dec 3, 2009
f34rbod
Posts: 2
Joined: Jul 19, 2009
Last seen: May 4, 2011
Hi everyone,

I would like to know where it's possible to get VHDL to Verilog code converters?
Any kind of help is appreciated.
RE: VHDL to Verilog
by arif_endro on Dec 4, 2009
arif_endro
Posts: 1
Joined: Jan 2, 2005
Last seen: Jun 15, 2015
You could use VASY from alliance tools, specify the output format to verilog output with command option -v.
RE: VHDL to Verilog
by jeremybennett on Dec 4, 2009
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

Hi f34rbod,

There have been a number of commercial attempts in the last decade, but none of them have been successful. They often work for small examples, but fail for large complex designs. There are a number of reasons for this:

  1. Verilog and VHDL both have complex, and in many cases poorly defined IEEE specifications. Ambiguities in the Verilog IEEE standard must be resolved by seeing how Verilog XL behaves. That is not a good basis on which to make a machine translation.

  2. Verilog and VHDL have different simulation semantics. It is extraordinarily hard to reconcile these, so simulations (and hence regression tests) are not consistent.

  3. VHDL is a bigger and more complex language than Verilog, so some constructs (for example assertions) do not have a true equivalent.

In practice this ceased to be a commercially worthwhile exercise once all the mainstream tools supported mixed Verilog and VHDL.

You will note that in the past IP providers like ARM provided all their IP in both Verilog and VHDL versions. Now they only provide a single language version, relying on tools to handle any language mixing required.

However this remains a problem for the open source community, since the existing tools (GHDL, Icarus Verilog, Verilator) are currently single language.

Daryl Stewart at the University of Cambridge (now at ARM) wrote his PhD dissertation on the formal semantics of Verilog and VHDL. I can't find it online, but you should be able to gain access to it through any University library. You may also like to look at Cambridge University Computer Laboratory Technical Report 485, Three notes on the interpretation of Verilog by Daryl Stewart and Myra Van Inwegen.

Sorry this doesn't give you a solution, but I hope it is useful background.

Jeremy

--
Tel: +44 (1590) 610184
Cell: +44 (7970) 676050
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RE: VHDL to Verilog
by jeremybennett on Dec 4, 2009
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

I have discovered that there is an archive copy of Daryl Stewart's work and the paper with Myra Van Inwegen online:

I understand this copy of the thesis is prior to its final corrections, so treat with the appropriate caution.

Jeremy

RE: VHDL to Verilog
by f34rbod on Dec 4, 2009
f34rbod
Posts: 2
Joined: Jul 19, 2009
Last seen: May 4, 2011
@arif_endro---thanks for the info. i will surely try it out


@jeremy---Now thats a very good insight into it. I appreciate your time and help.

Thank you both of u :)
RE: VHDL to Verilog
by i on Jun 16, 2010
i
Posts: 2
Joined: Jun 15, 2010
Last seen: Jun 17, 2010
Hi,

I'm looking for translator from VHDL to Verilog.
I have a code written in VHDL and I need to translate it to Verilog.
Maybe you used one?
Please, any help is good help.

Thanx
RE: VHDL to Verilog
by Fylden on Jun 22, 2010
Fylden
Posts: 1
Joined: Jun 21, 2010
Last seen: Dec 5, 2010
There is no approach except for how to learn VHDL. But when you will learn you can write in both languages using their strengths.
RE: VHDL to Verilog
by rahulm_vlsiaug08 on Dec 18, 2012
rahulm_vlsiaug08
Posts: 1
Joined: Feb 17, 2009
Last seen: Jan 7, 2013
ML_LFSR.vhd (1 kb)
RE: VHDL to Verilog
by kharthik on Feb 1, 2013
kharthik
Posts: 2
Joined: Feb 1, 2013
Last seen: Oct 31, 2019
Hi everyone,

I would like to know where it's possible to get VHDL to Verilog code converters?
Any kind of help is appreciated.
8b10_dec.vhd (7 kb)
RE: VHDL to Verilog
by AbhiGondaliya on Feb 24, 2016
AbhiGondaliya
Posts: 1
Joined: Nov 23, 2015
Last seen: Jun 7, 2016

I have discovered that there is an archive copy of Daryl Stewart's work and the paper with Myra Van Inwegen online:

I understand this copy of the thesis is prior to its final corrections, so treat with the appropriate caution.

Jeremy

vhdl code.txt (1 kb)
RE: VHDL to Verilog
by sanjeevreddi on Mar 15, 2016
sanjeevreddi
Posts: 2
Joined: Mar 12, 2016
Last seen: Jun 27, 2016

Hi f34rbod,

There have been a number of commercial attempts in the last decade, but none of them have been successful. They often work for small examples, but fail for large complex designs. There are a number of reasons for this:

  1. Verilog and VHDL both have complex, and in many cases poorly defined IEEE specifications. Ambiguities in the Verilog IEEE standard must be resolved by seeing how Verilog XL behaves. That is not a good basis on which to make a machine translation.

  2. Verilog and VHDL have different simulation semantics. It is extraordinarily hard to reconcile these, so simulations (and hence regression tests) are not consistent.

  3. VHDL is a bigger and more complex language than Verilog, so some constructs (for example assertions) do not have a true equivalent.

In practice this ceased to be a commercially worthwhile exercise once all the mainstream tools supported mixed Verilog and VHDL.

You will note that in the past IP providers like ARM provided all their IP in both Verilog and VHDL versions. Now they only provide a single language version, relying on tools to handle any language mixing required.

However this remains a problem for the open source community, since the existing tools (GHDL, Icarus Verilog, Verilator) are currently single language.

Daryl Stewart at the University of Cambridge (now at ARM) wrote his PhD dissertation on the formal semantics of Verilog and VHDL. I can't find it online, but you should be able to gain access to it through any University library. You may also like to look at Cambridge University Computer Laboratory Technical Report 485, Three notes on the interpretation of Verilog by Daryl Stewart and Myra Van Inwegen.

Sorry this doesn't give you a solution, but I hope it is useful background.

Jeremy

--
Tel: +44 (1590) 610184
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com

8b10_enc.vhd (9 kb)
RE: VHDL to Verilog
by sanjeevreddi on Mar 15, 2016
sanjeevreddi
Posts: 2
Joined: Mar 12, 2016
Last seen: Jun 27, 2016
Hi everyone,

I would like to know where it's possible to get VHDL to Verilog code converters?
Any kind of help is appreciated.
8b10_dec.vhd (7 kb)
RE: VHDL to Verilog
by aikijw on Mar 15, 2016
aikijw
Posts: 76
Joined: Oct 21, 2011
Last seen: Mar 25, 2020
If the attached code is the code you are looking to convert, then the only help I can offer you is to suggest that you just translate it by hand... The process should take about an hour, worst case...


Hi everyone,

I would like to know where it's possible to get VHDL to Verilog code converters?
Any kind of help is appreciated.
8b10_dec.vhd (7 kb)
benchmark circuits
by sakshee25 on Jan 28, 2017
sakshee25
Posts: 1
Joined: Jan 15, 2017
Last seen: Apr 5, 2019
Hii everyone.
I want description and verilog code of IWLS'05 benchmark circuit.Please someone tell me.
RE: VHDL to Verilog
by 6HJS on May 13, 2017
6HJS
Posts: 1
Joined: May 23, 2016
Last seen: Sep 9, 2018
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity Top is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0);
MemOE : out STD_LOGIC;
MemWR : out STD_LOGIC;
FlashCS : out STD_LOGIC;
FlashRP : out STD_LOGIC;
MemAdr : out STD_LOGIC_VECTOR(26 downto 1);
MemDB : inout STD_LOGIC_VECTOR(15 downto 0)
);
end Top;

architecture Behavioral of Top is
signal slow_clock : STD_LOGIC;
signal led_reg : STD_LOGIC_VECTOR(7 downto 0);
signal state : unsigned(3 downto 0) := "0000";
signal state_next : unsigned(3 downto 0);
begin

led
-- Clock Generation
clock_core : entity work.ClockCore
PORT MAP
(
clock => clock,
clock_3375 => slow_clock, -- 3.375 Mhz clock
RESET => reset
);

process (slow_clock, reset)
begin
if (reset='1') then
state led_reg elsif (slow_clock'event and slow_clock='1') then
state if (state = "1110") then
led_reg end if;
end if;
end process;

MemAdr MemDB MemWR FlashRP
process (state)
begin
case state is
when "0000" =>
-- initialize
FlashCS MemOE when "0001" =>
-- enable flash
FlashCS MemOE when "0010" =>
-- enable flash output
FlashCS MemOE when others =>
-- hold steady
FlashCS MemOE end case;
end process;

state_next
end Behavioral;
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