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SystemVerilog
by head_up on Feb 26, 2010 |
head_up
Posts: 4 Joined: Nov 10, 2008 Last seen: Nov 23, 2024 |
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Hi! i have some experience with Verilog and i'm looking for a high-level language (for design and verification). At first time SystemC look to be a good choice but more for verification, not for design. Can u help me: is SystemVerilog language with feature in design? after research i understood - it is prefered as a Verification language, but i have no more observations. thanks in advance :)
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RE: SystemVerilog
by head_up on Feb 28, 2010 |
head_up
Posts: 4 Joined: Nov 10, 2008 Last seen: Nov 23, 2024 |
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in addition: Do You know whether Xilinx plans to support SV in the near future (ISE 12 for example)?
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RE: SystemVerilog
by socrates on Mar 19, 2010 |
socrates
Posts: 1 Joined: Feb 17, 2009 Last seen: Sep 14, 2023 |
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Maybe You could ask Xilinx and reply here? :)
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