Hi everybody.
Does someone know where to learn about WishBone bus, I've downloaded WishBone specifications, but it was not succesufully for me to learn "How To use" this bus specification.
I mean, simply, if you should assert ie: Strobe_i line, when you want to enter some byte from the data_i line. Does this work always in the same way for any core that is WishBone compatible ?
Does this work like I explained below ?
Should I consider that bus similar like a SRAM chip ?
Where to find responses for this begginer questions ?

Thanks in advance.
Alberto.

Hello,
I also had a first look into the Wishbone specs. and think you are right. But keep in mind that there is the access acknowledge line. If your Wishbone member uses more than one clock to handle you must delay your acknowledge. Other vice when one clock is sufficient it can be connected to the access line.

Thank you man.
I will do a first try, and then ask again if not success.
Regards.
Alberto.

what does "more than one clock to handle" mean ?