hi,

i'm doing an FPGA development.
this fpga communicates to an external SoC through a 32-bit bus.

the 32-bit bus has the following characteristics:
- nCS for chip-select
- typical nWE for write-enable and nOE for read-enable
- when LBA is asserted, the address is on this 32-bit bus
- otherwise, 32-bit data (either write-mode or read-mode) is on the bus

the FPGA is to communicate from/to this bus asynchronously.
could you help if my synchronization scheme is robust enough?

- ALL of the above signals (ie. nCS, nWE, nOE, LBA, 32-bit bus) go through synchro double-ff
- the 32-bit data wait-state is adjustable
- but the LBA max-assertion time is: 1.7 clock-cycle of FPGA clock
is this a problem?
- I created 'address_valid' by using edge-detect circuit based on 2 outputs:
-> the 1st flop stage of synchro double-ff
-> and the 2nd flop stage of synchro double-ff
- only when 'address_valid', which is 1-clock-wide, I latched the address

thanks a bunch...

Hi rdelario,

You cannot use the output from the first stage of the syncronization flip-flops for edge detection (or for anything else for that matter). That signal may be metastable, so if you use it, your design will be unreliable.

If you want to do edge detection, you have to add yet another flip flop, which delays the detection of edges by one clock cycle. At that time, the 32-bit bus may not have a stable value any more. To compensate for that, you could add yet another flip-flop stage to all the other signals as well, but that costs a lot of flip-flops. So I wouldn't recommend edge detection in the traditional meaning.

Instead, create a combitorial signal that detects when nCS and LBA is active. Then register that signal. When the combinatorial signal is true (or '1' or whatever), and the registered signal is not, then latch the address.
This is similar to the traditional edge detection method, but it reacts one cycle earlier, so you don't have to look at the first stage of the syncronizing flip-flops.

If LBA is active 1.7 cycles, it means that it will be detected for at least one FPGA cycle, which is enough.

It is also required that value of the 32-bit bus is stable for at least one FPGA clock cycle before and after the LBA cycle.

There may be other things to think about, see the waveform diagrams in the SoC's data sheet or manual.

Good Luck