Guys I am new at VHDL. Can anyone tell me how to find maximum operating frequency of a Xilinx ISE vhdl design ?

Hello,
Please go through the synthesis report.It will contain timing summary of your design.
A sample is given below.


Timing Summary:
---------------
Speed Grade: -7

Minimum period: 7.955ns (Maximum Frequency: 125.709MHz)
Minimum input arrival time before clock: 10.297ns
Maximum output required time after clock: 4.276ns
Maximum combinational path delay: 4.773ns

I think this may help you.The maximum frequency of operation is determined by the path with provide maximum delay.

Thanks for the reply. Which version of ISE are you using ? and how can I reach this synthesis report? Thanks again.