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problem with module_defines.v statement in UART module
by bujjibabup on Nov 23, 2010 |
bujjibabup
Posts: 2 Joined: Nov 21, 2010 Last seen: Nov 6, 2017 |
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hi every body
i got a code from opencores for UART with FIFO but i m getting errors with first and second statements: `include "timescale.v" `include "module name defines.V" plz let me know the replacement for those two instructions and to avoid warnigs
522079428_533342_SEP2010.pdf (46 kb)
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