Hello Olivier,

My name is Shilan Parsaeian. I am a M.Sc. student. For evaluation of my thesis I should synthesis my case study processor, but I do not have standard cell library and I am beginner in Design Compiler. Would you please help me? Any help from you wuld appreciated. How can I complete library.tcl (Define worst case library, Define best case library, Define operating conditions, Define wire-load model, Define nand2 gate name for aera size calculation). Can you send me these standard cell libraries for 0.18um?

Best Regard
Shilan Parsaean

Hi Shilan,

Glad to hear that you chose the openMSP430 as a part of your M. thesis :-)

Regarding your synthesis problem, I guess that if your university owns a Design Compiler license, then it also has some libraries laying somewhere... your tutor probably knows about what's available on your side.
Now, concerning the "synthesis.tcl" script update, the bottom line is that you'll have to look for these information in the library documentation you'll get from your university.

For the worst case library (typically characterized for low voltage and high temperature), you'll have to specify the DB file name and the library name. The same needs to be done for the best case library (typically characterized for higher voltage and low temperature).
This could for example look as following:
"...
# Define worst case library
set LIB_WC_FILE "my_worst_library_file.db"
set LIB_WC_NAME "my_worst_library_file.db:slow"

# Define best case library
set LIB_BC_FILE "my_best_library_file.db"
set LIB_BC_NAME "my_best_library_file.db:fast"
..."

Operating conditions and wire-load models values needs to be picked up from the documentation.

Finally, the nand2 gate name is used in order to calculate the number of kgates based on the final area report. This means that you should here select the smallest nand2 gate of your library. Typically, in all TSMC libraries I had to deal with, this gate is called NAND2X1.

I hope this was helpful.

Good luck with your thesis,
Olivier