hello,
I've downloaded the vhdl code for i2c controller interfacing with wishbone.
but i am unable to get idea about scl_pad_i and all other i2c lines..
should my main SCL line is scl_pad_o ? (and sda_pad_o is main SDA line ?)....
And where should i give data to be transmitted to SDA? plz help......

I2C uses open drain outputs on all devices attached to the bus. Separating input and output for clock and data serves for example the purpose to detect bus hazards. For example: Your controller writes a logic '1' to the data line (sda_pad_o most likely) yet reads a logic '0' from sda_pad_i (both attached to the same physical line) your controller knows that some device on the bus is itself writing and not reading as it is supposed to.

Thanks for reply.
I m using
1.DAC (mcp4725) as a slave.
2.8051 micro controller to control and data transfer between internal registers like Prer,Command,Control,etc

I m giving micro controller frequency (i.e.11.0592Mhz) to wb_clk_i port.
I m confused what clock i should give to scl_pad_i and should i give data to sda_pad_i or transmit register through micro controller.
In documentation they have given to write code for tri state buffer.
but i haven't found such code in downloaded .vhd
plz plz help me. i am doing this project for my third year final exam.

Thanks for reply.
I m using
1.DAC (mcp4725) as a slave.
2.8051 micro controller to control and data transfer between internal registers like Prer,Command,Control,etc

I m giving micro controller frequency (i.e.11.0592Mhz) to wb_clk_i port.
I m confused what clock i should give to scl_pad_i and should i give data to sda_pad_i or transmit register through micro controller.
In documentation they have given to write code for tri state buffer.
but i haven't found such code in downloaded .vhd
plz plz help me. i am doing this project for my third year final exam.