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How to write a benchmark under Verilog?

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How to write a benchmark under Verilog? by 418ImATeapot on May 4, 2011			418ImATeapot Posts: 2 Joined: Apr 22, 2011 Last seen: Mar 27, 2014
Hello world!! Can anybody tell me how to write test-modules for Verilog. I now use Icarus under Win32. Sorry for my English. Thank you. Hello world!! Can anybody tell me how to write test-modules for Verilog. I now use Icarus under Win32. Sorry for my English. Thank you.

RE: How to write a benchmark under Verilog? by richard_vlamynck on May 6, 2011			richard_vlamynck Posts: 31 Joined: Sep 15, 2008 Last seen: Jan 24, 2016
[q]Hello world!! Can anybody tell me how to write test-modules for Verilog. I now use Icarus under Win32. Sorry for my English. Thank you.[/q] A test-module by another name is a test-bench. A test bench should exercise all of your modules inputs and outputs for legitimate values. Does that help answer you ques8tion? Regards, RichV. Hello world!! Can anybody tell me how to write test-modules for Verilog. I now use Icarus under Win32. Sorry for my English. Thank you. A test-module by another name is a test-bench. A test bench should exercise all of your modules inputs and outputs for legitimate values. Does that help answer you ques8tion? Regards, RichV.

RE: How to write a benchmark under Verilog? by 418ImATeapot on May 6, 2011			418ImATeapot Posts: 2 Joined: Apr 22, 2011 Last seen: Mar 27, 2014
[q][q]Hello world!! Can anybody tell me how to write test-modules for Verilog. I now use Icarus under Win32. Sorry for my English. Thank you.[/q] A test-module by another name is a test-bench. A test bench should exercise all of your modules inputs and outputs for legitimate values. Does that help answer you ques8tion? Regards, RichV.[/q] Thank you, but I had problems with trying to write it as a normal module with non-sintesys instructions. The simulator stopped or went into a infinity loop. From examples in Internet, I understood, that I must use #[number]. But when and how? Hello world!! Can anybody tell me how to write test-modules for Verilog. I now use Icarus under Win32. Sorry for my English. Thank you. A test-module by another name is a test-bench. A test bench should exercise all of your modules inputs and outputs for legitimate values. Does that help answer you ques8tion? Regards, RichV. Thank you, but I had problems with trying to write it as a normal module with non-sintesys instructions. The simulator stopped or went into a infinity loop. From examples in Internet, I understood, that I must use #[number]. But when and how?

RE: How to write a benchmark under Verilog? by fatihhamurcu on Jul 26, 2011			fatihhamurcu Posts: 1 Joined: Jul 25, 2011 Last seen: Aug 16, 2013
You should use paper before starting to write a testbench. I will tell you how to write test bench step by step. - always #X clock = ~clock determine X - determine your verilog code inputs and outputs - create one module with your project, like creating an object in c++ - # Y, for each Y time, change your input and monitor the output - Do not forget inertial and transport delay when determining Y You should use paper before starting to write a testbench. I will tell you how to write test bench step by step. - always #X clock = ~clock determine X - determine your verilog code inputs and outputs - create one module with your project, like creating an object in c++ - # Y, for each Y time, change your input and monitor the output - Do not forget inertial and transport delay when determining Y

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