Hi,

I am used to IP development and integration in Microblaze/PPC based designs.

I use Xilinx FPGAs hence using Xilinx tools.

I am interested in open-source hardware, but I have no Idea how to program an FPGA without the FPGA manufacturer tools.

would you please explain me briefly the design flow for a simple SoC(on wishbone bus), specifically the design upload to the FPGA step.

Thank you

you can do quite a lot of things with opensource software. but there is no complete workflow possible yet.

do you write verilog or vhdl?

there are nice editors around for hdl programming. currently the best one i know for vhdl is emacs. in fact i use emacs only for vhdl.

simulation can be done also with opensource tools, for verilog there is icarus, also used for the openrisc (personally i have no experience with verilog).
for vhdl there are at least two simulators around ghdl and freehdl.
you can also look at the alliance http://www-asim.lip6.fr/recherche/alliance/ project, a complete vlsi development suit.

the steps par, map and route are not possible with opensource tools for fpga's (you CAN draw your asic with open tools), for this steps you need the vendor tools.

the output from the vendor tools is normaly something in binary format. all fpga vendors give you the possibility to convert the fpga bitstream into an SVF (standard vektor format) file. most jtag programming tools allow you to "playback" a svf file on a specific device.

thats how you download your design to your fpga. generate the svf file and use for example urJTAG to download it. http://urjtag.sourceforge.net/

The simple answer is that vendor tools are required for back-end mapping, placement and routing.

Good luck.