Hello guy's, I have a small problem with a concatenation in vhdl.
I will post the code :
[code]Router_Nr_West i_data_vest
where DATA_TO_BE_ROUTE_NORTH_IN : in std_logic_vector(31 downto 0);
signal Router_Nr_West : std_logic_vector(7 downto 0);

I worck with a NanoBoard NB2 and Altium Designer Winter 09 and I am stuck at the simulation because the i_data_vest will have a value without the
Router_Nr_West. I attached a photo to ilustrate.

Thank's in advance.

Hi fantomas2002ro,

Without a little more information it's hard to determine what is exactly going on. It might be that the signal Router_Nr_West hasn't had time to be evaluated before being concatenated in the next step.
This would mean that the updated value (with + X"01"), will not propagate.

Try adding a delta delay to the Router_Nr_West assignment signal?

Have you tried another similar assignment statement? For example:

i_data_vest
If you posted more of the code, it might be easier to determine the issue.

Hope this helped.

I agree with julianmilthorpe, it seems you are expecting the signal assignment to take place instantaneously. The VHDL simulator engine will only effect the change in the next delta-cycle.
If you are describing sequential logic (a clocked process), that concatenation will take place on the "old" values, i.e., the results from the previous clock cycle.
If you are describing combinatorial logic, the process must have all the signals in the sensitivity list, and the concatenation will only be reflected in the "next" iteration, generally meaning that you will have a propagation delay in physical circuitry.

Can you please post at least the complete process around the assignment?