Hello,

I think I have a easy problem (for you not for me :-) ).

I have a ADC with 14 bit resolution. The interface is serial:
- DDR data
- dco
- fco

My FPGA is a Xilinx Virtex 5 fx30.

What is the best way for deserializing the data?

I'm not sure I understand the interface. Can you give me a link to the data sheet for the ADC, or can you explain a bit more what the three signals do.

Of course

Here is the link to the ADC

http://www.analog.com/static/imported-files/data_sheets/AD9252.pdf

On the first page in the picture you can see the "DATA RATE MULTIPLIER". CLK+ and CLK- are inputs. FCO+-, DCO+- and D-A...H +- are outputs.

On page 8 (PDF reader page 7) is the transfer shown.
The transfer from the ADC is:
- serial
- double data rate
- differential

DCO is the data clock and fco is the frame clock.

What is the best way for parallelizing?

I think the first step is a "IBUFDS" :-)

Yes, the first step is to use an ibufds

To create a single rate signal you can do something like this in VHDL. Guess it's something with always @posedge/negedge in verilog.

if rising_edge(dco) then
dpos elsif falling_edge(dco) then
dneg end if;

To do the paralellization, you could then use something like this:
process(dco)

begin
--create a counter that is reset every time you got a rising edge on fco
fco_r if fco = '1' and fco_r = '0' then
cnt else
cnt end if;

--Write the two last received bits to a vector.
--The bit positions are specified by cnt, and when a frame is received, it is output to paralell_data
buf(cnt) buf(cnt+1) if fco = '1' and fco_r = '0';
paralell_data end if;
end process;

Just a rough sketch. It won't work, but might give you some ideas.

Many thanks to you! I will try it tomorrow.