Hello,

I am new to VHDL and am trying to work through a simple design and testbench. This is propbably a stupid question but any help would be greatly appreciated.

I am trying to get my testbench to react to a change in state in the model. The device simulates fine and works when I instantiate it in the FPGA. In simulation I can drive all of the I/O but I would like my testbench to drive a conditional reset to simulate interaction with the uCNTRLR after count completion. Everything works fine except I can not detect that transition of the model port OG_TX_Complete even though I can see that it is transtioning in Model Sim. I have tried everything I can find to no avail. Thanks in advance for your help.

Randy,

A stub of pseudo-code is:

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

constant SYSCLK_PERIOD : time := 25 ns;

signal END_LOOP : std_logic := '0';

component Beacon_FPGA
-- ports
port(
-- Inputs
--various signals declared here

-- Outputs
--various signals declared here

OG_TX_Complete : out std_logic; -- this signal is the one that goes high and I could like to condition on

-- Inouts

);
end component;

begin

main: process
variable vhdl_initial : BOOLEAN := TRUE;

begin

if ( vhdl_initial ) then

-- Some junk which causes port OG_TX_Complete to go high

end if
--loop through once
wait;

end process main;

--stop when loop complete
end_loop_Proc: process
begin
-- code that will stop the main process
wait until END_LOOP = '1';

end process end_loop_Proc;

-- port map
port map(
-- Inputs
- signal to port assignmnets here

-- Outputs

OG_TX_Complete => END_LOOP, -- The assignment I am trying to use to allow detection of the OG_TX_Complete transition from low to high

-- other signal to port assignments

-- Inouts

);

end behavioral;