Some would claim that Verilog is a better language than VHDL

Would anyone care to comment one way or another?

This is one of the holy wars starter subject. If you're interested google "Verilog vs VHDL" to get a sample of some flaming discussions.

That said, I think you have to learn both languages. The major professional EDA toolchains support both, and some serious no-cost tollchains (like Xilinx ISE) do that also.

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I prefer VHDL for large projects, and the methodology I use in company uses VHDL.
In VHDL I like:
- strong typing, that enforces good data description and data modeling;
- generic parameterization of modules, that leads to design re-use from start;
- strong data hiding and abstraction, that facilitates multiple instantiations;
- explicit parallel processing model, that enforces hardware design view and visualization;
- signal and transaction-oriented transfer model, that avoids "software-like" mistakes like multiple bus drivers;
- very high-level data abstractions, with structured records and user type definitions, that increase clarity of functional description at the RTL level;
- strong port interfaces, that allows more maintainable and verifiable circuit blocks;
- formal descriptions that allow very good control over inference engines without resort to low-level structural instantiation of vendor libraries;
- very powerful testbenches, with file i/o and high-level test vector data modeling;
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On the other hand, Verilog is supported by a larger base of open-source tools and simulators, and is used by a larger IP vendor base.
In Verilog I like:
- lower-level descriptions, very similar to low-level C code;
- easier to learn by "software people";
- preprocessing-like style of macros;
- global vars enable state monitoring without explicit debug ports;
- easier description of very low-level digital circuitry, at the macrocell and gates level;


Disregarding market preferences and usage, I chose VHDL for the methodology used in my hardware design group because it tends to enforce reusable model writing, can lead to functional clarity and is more maintainable in the long run, i.e., you get less clutter code from several developers doing maintenance on existing models.

Disregarding market preferences and usage, I chose VHDL for the methodology used in my hardware design group because it tends to enforce reusable model writing, can lead to functional clarity and is more maintainable in the long run, i.e., you get less clutter code from several developers doing maintenance on existing models.
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VHDL is a great language for representing a design but a lousy one for entering it. If you compare any circuit in VHDL vs the same thing in VERILOG then the VHDL will be 3 to 5X the size. All that typing takes its toll and slows down the design process.

A lot of people compare VERILOG to C but it also uses the *NIX philosophy. A lot of small simple tools that each do one thing well. The user can chain these tools together as they see fit.

All those "advantages" that you see in VHDL can be duplicated in VERILOG by adding preprocessors and rtl checkers. The only thing VHDL does is to build them into the language and force their usage on everybody.


A VERILOG car has a tire check accessory that measures pressure in all four tires and the spare. If you neglect to run it at the wrong time you can wind up stranded.

A VHDL car will not start the engine until after you have performed that check. You have a lot less chance of breaking down but you pay a price every time you go somewhere.


Managers like to select VHDL for their minions because it ensures that the code meets a certain minimum level of quality. To get that from VERILOG a manager actually has to do some real work. They have to understand and create a design standard, set up tools and processes that will catch problems and have enough staffing to do the project with out cutting corners.





John Eaton

I thank you both for your prompt responses and articulate answers.

I was in no way trying to provoke a flame war but simply hoping to evoke a response. I had posted an earlier question about the differences in these languages and why anyone might chose one against the other. This post got 33 views and no answers.

I am a big fan of type safety so I can see the benefit of that built into the language. I shall concentrate my efforts on VHDL first. I'm sure that at some point I shall pick both languages up.

Regards
Marc