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Verilator and VHDL
by sebx86 on Sep 7, 2011 |
sebx86
Posts: 11 Joined: Sep 19, 2008 Last seen: May 16, 2020 |
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Hi all,
I have been working for a while on the Verilator compiler to add support of VHDL93 (to begin), some things are supported but it's not ready for serious use yet... You will find the current development status here : https://github.com/sebx86/VerilatorVHDL Current development limitations: - One VHDL file (1 entity, 1 architecture only) - If not totally supported yet - No clocked process - No select - No for - No case - No functions/sub - No instanciation I hope to solve all those issues to go back mainstream for end of december... I also plan to support custom types and records in the beginning of next year. Definitive limitations: - Synthesizable constructs only - Cycle accurate models (RTL, no delay statements) - Wait statement not supported Any feedback is welcome. |
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RE: Verilator and VHDL
by olof on Sep 7, 2011 |
olof
Posts: 218 Joined: Feb 10, 2010 Last seen: Dec 17, 2018 |
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This is very welcome news. There aren't very many free VHDL tools available. Keep up the good work! I will give it a try when I have time
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