As a total newbie I do need some help. And looking through forums or other internet sources I have not found suitable answers. So some pointer would be very welcome.
I do have experience designing logic. But this is with TTL chips.
My problem: I have a Gal 16V8 design and the Jedec file. These work fine.
But I want to make some changes and do simulation.
For this I try to use Atmel WinCupl.
I've had different designs for this working fine, including the simulation.
But this particular stuf I can't get done.
It's like the clock is not connected to the counter in the WinCupl design.
Help please.
Below is the part that works, the non working but is attached.

*IDENTYFICATION
clk_man;
*TYPE
GAL16V8
*PINS
PHI1S = 2,
PHI1F = 5,
SLOW = 6,
Reset = 7,
Halt = 8,
RDY = 3,
RW_in = 9,
Q0.r = 16,
Q1.r = 17,
Q2.r = 15,
PHI1.t = 18,
Clock.t = 19,
Bank_L.t = 13,
RW_out.t = 14,
A_Bus_EN.t = 12;

*BOOLEAN-EQUATIONS
/Q2 = /Q1 & Q0 & Reset;
/Q1 = /Q1 & Q0 & Reset + Q2 & /Q0 & Reset;
/Q0 = Q2 & Q1 & Reset + /Q2 & /Q1 & Q0 & Reset;

Clock.e = Vcc;
Clock = Q2 & Q1 & Q0 & SLOW & /PHI1 + Q2 & Q1 & /Q0 & PHI1F
+ Q2 & /Q1 & /Q0 & /PHI1F + Q2 & /Q1 & Q0 & /SLOW & /PHI1
+ /Q2 & /Q1 & Q0 & PHI1S + /Q2 & /Q1 & /Q0 & /PHI1S
+ /Reset;

%Outputs%

PHI1.e = Vcc;
PHI1 = Q2 & Q1 & Q0 & PHI1S + Q2 & /Q1 & Q0 & PHI1F;

Bank_L.e = Vcc;
/Bank_L = /PHI1 + /RDY;

RW_out.e = Vcc;
/RW_out = Q2 & Q1 & Q0 & Halt & /RW_in
+ /Q2 & /Q1 & /Q0 & Halt & /RW_in;

A_Bus_EN.e = Vcc;
/A_Bus_EN = Q2 & Q1 & Q0 & Halt + /Q2 & /Q1 & /Q0 & Halt;
*END