Actually the Problem is that I have a design of SPADIC (ASIC) chip. It has Filters, FIFO's and Buffers. I have a testbench as well added in the top module. Everything in the simulation is working well. There are simulation FIFO's and core generator FIFO's but at the moment I am using Simulation FIFO's. The output of the whole thing is a Pulse which has a shape of 0 10 40 45 38 28 20 ..................... 0. So it started from 0 and It should and ended at 0.

The problem I am facing at the moment is that The output in the consol is like 10 10 40 which should be 0 10 40. so 10 is repeated somewhere in the logic. This is the only problem I am facing. Rest of the stuff is OK.

Pulse generator is the output of ADC's as there is no physical ADC connected and then this pulse passes through the HIT logic, filters and Buffers and at the output we have 0 10 40 45 38 .................. 0. we just need to see signals in the simulation that where this 10 is repeated. Please reply as soon as possible