hiii i am a newbee to vhdl coding.. please help me with the following problem. I have written a code in VHDL to count the no. of rising edge of 1 MHz clock in the time period when another input clock generates a total of 8 ticks. On runnin the code in continuous mode...most of the time i am getting correct values but sometimes i get less values of count. For eg. if i give a 333Hz signal as input i should ideally get 24000 as output. Most of the time i get that, but sometimes i get values as 22500, 21000, 19500, 18000. Please lemme know if i am doing something wrong. I am getting these warnings while synthesizing the code.

Route 447 : clk Net : time_up may have excesive skew because 9 non clock pins failed to route using a clock template.

Gated clock: clock_1MHz is sourced fom a combinatorial pin. This is not a good design practice. Use CE pin to control loading of data into flip flop.

however i have used similar method to extract another clock where i am not getting any such warning.

I have attached the code for reference.

Hello,

You should think about using synchronous logic.
Line 95 is the origin of your gated clock, this should never be written this way. If you want to divide by 4. See other VHDL examples for 2 bits counter.

When I look at your code, I see lots of flops that are driver by at least 4 different clocks. I don't think it's what you want. On the pulse in, you should not use the edge detection, at least it should not done this way.

You should use only the 10M clock and make edge detection on the pulse_in depending on the 10M clock.

ie (just to give you an idea, this is not especially valid VHDL)

signal prev_Pulse: std_logic;
signal counter: std_logic_vector (15 downto 0);

process (clk)
if clk'event and clk='1' then
if pulse_in = '1' and prev_Pulse = '0' then
counter end if;
prev_Pulse end if;
end process;

I think it will solve a big part of your problems...