Hi,
Is it possible in verilog to write a structural implementation of master slave D- flipflop using a D-flipflop code written earlier? (the flip flop is edge triggered)

Yeh I think should be easy to do.

If it's an structural module you must have module instance as d_ff (inp, clk, rst, enable, out)

you take two instance of d_ff and take NOT of enable signal from previous one and feed it to the other instance.

d_ff(inp, clk, rst, enable, out1);
d_ff(out1, clk, rst, ~enable, out);

there you've a master-slave flip-flop