Hi, I have been working on a project with the T80 core as the processor. I have a DE1 Altera board. When I map the 50Mhz crystal to the GPIO so I can look at it on the scope it is only 1vpp. Is this voltage normal. When I divide it down to 3Mhz the clock I use to run the T80 core it is 3.3vpp what I expect. So my question is kind of general and is the following. Should I not be using the 50Mhz to sync up the peripherals ?

Does some one know where I could find details on clocks in FPGA design and maybe how to start up this system on power up ?

Thanks for your replies in advance.

Two thoughts come to mind:

1) The I/O pin you're using isn't capable of driving a 50 MHz signal to 3.3V due to insufficient output drive, excessive capacitance, or slew rate limiting.

2) The device you're using to measure the signal isn't fast enough to respond to a 50 MHz signal. What is the bandwidth of your 'scope?

Yes, thanks it more than likely is one of those two. I just needed someone to tell me. I feel better. :-)