Dear All,

I'm trying to simulate the A VHDL 16550 UART core from the projects and found some files are missing
in the zip file the link from where i had downloaded the project is http://opencores.org/project,a_vhd_16550_uart

The project status says its complete and stable but the files listed below are missing in it.

1. gh_edge_det.vhd
2. gh_register_ce.vhd
3. gh_DECODE_3to8.vhd
4. gh_jkff.vhd
5. gh_baud_rate_gen.vhd
6. gh_counter_down_ce_ld_tc.vhd
7. gh_edge_det_XCD.vhd

I request if some one has these file and test bench to simulate the UART code to please share it across.

Thanks & Best Regards,
Chetan.