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no use no use 1/1 no use no use
Newb question
by jonconnell on Mar 19, 2013
jonconnell
Posts: 1
Joined: Aug 23, 2012
Last seen: Mar 19, 2013
Silicon level / development board advice please:

I am tinkering with multiple PIDs for low power control, used in combination with multiple PWM outs for subsequent external device control and most importantly just a ton of rather busy timers doing various complicated things plus an RTC. Say ~under 10 fast PID control loops and less than 10 PWM out on some GPIO.

Basically I am managing dc power in the
Question:

1)Suggest a development board for me to play with.
2)Suggest any resources covering power control / PID from FPGAs?


Goal is to get myself to an highly configurable system based on re-usable IP blocks - and hopefully eventually a very low cost and versatile commerical design. Most importantly one configurable on the fly and by others. (and some day by other machines I hope).

I am loving the IP re-use concept - fundamental to how I like to work. Works very well with my plans for commercialization of a turn-of-the-wheel new product. Consumer equipment. Research only today.

Background:
Based on my own R&D in creating PID control loops on low cost micros versus the performance of dedicated standard single ic micro SOCs with onboard PID solutions, sample speed seems to be important - hence my looking here. Speed: No exact spec on that today, but a good SMPS design in my world seems to sit around 1MHz these days. (The output I am PIDing that is...) Seems to me from experiment that I need higher sampling rates than I can get out of lowest cost micros - which is not what some text books tell me.

(I can see a nice looking PID block and also some useful PWM blocks in projects here already).

The solution I need is well-enough covered in conventional and hybrid analogue devices today. Issue is scale of my application ends up with some relatively expensive silicon in order to handle all the necessary timers and the on-the-fly computation plus a ton of pricey analogue parts to implement the power control.

The sheer complexity of the timers arising from second higher level of the end-application make this a bear to put onto low cost micros. I figure a better programmer could probably get a mid-range Arm to do what I want well enough, but there's more fun in doing this on an FPGA and I have a strong feeling a sound financial reason too - at least eventually. Wiring and configs that I can send over a wireless jump seems more 21st century to me and likely more commercially useful.

Oh, I will need the usual interfaces to the outside world - but in production probably just one wireless jump of some flavor tbd to whatever the PDA of choice is that year. Slow stuff. The power control is the only fast application.


Me, just FYI: EE degree - 30 years out of date though.VHDL novice. Can write a little C. Can edit up a storm in almost anything. Independent so open source is a benefit. Understands(ish) FPGA and SOC concepts a little. Has access to a copy of Altium Designer. Understands the engineering mathmatics as applied to real-world software design well enough, just a tad too long out of school.
no use no use 1/1 no use no use
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