Hi

I want to check if an inout port xx as the strength/value SUPPLY0, SUPPLY1, etc.

I use Modelsim for Verilog compliation

When I try
if (xx == SUPPLY0)

I get a compilation error.

Could anyone help me on that, please?

Thanks

Hi,


As for as my knowledge design which uses If loop is called as behavioral level design.

Also we should not "MIX" Behavioral level with Switch level modeling. I guess. !!

In your program "xx" is an inout port and according to the behavior(xx== SUPPLY0) of that port ("xx") if loop works.

Are you sure IF loop works in SWITCH level modeling ?

How do u represent IF in switch level modeling?

xx == SUPPLY0 => means your checking physical GND with INOUT port signal

Technically speaking i say its wrong that's why you getting compile error !!

logically if( something == something ) syntax is correct, so no error.

This is what i know.
If this is not correct. anyone know the answer correct me.

Thanks.

This is not a loop IF, though. To make it clearer, here are two examples where I get compilation errors:

example 1:
==========
inout a;
wire b;
assign b = (a == SUPPLY0)? 1'b1: 1'b0;

example 2:
==========
inout a;


always @(*)
if (a == SUPPLY0) $display("a state is supply - 0");


both examples do not compile

WHY???

Hi,

what is the compilation error that you get? and what is the TYPE or SUPPLY0.

The failing code line is:

wire mirror = (supu_io == supply0)? 1'b1: 1'b0;

supu_io is declared a the top:

inout supu_io;


The Modelsim compilation error message is
...: near "supply0": syntax error, unexpected supply0

Thanks

Hi..

You are comparing a WIRE value to a DATA-NET ????

supply0 is a SAVED datatype for chip power supply.. it is NOT A VALUE.

the same way you do
inout a;
wire b
etc..

you must do:
supply0 gnd

here you are defining a new "wire" which is power-supply NET (ground).

In short you must do the following:

inout supu_io;
supply0 gnd;
wire mirror = (supu_io == gnd)? 1'b1: 1'b0;


Hope this helps you

but by the way..

i think doing so is extremely stupid.. you never check an inout to gnd value..

The good thing about this suggestion is that I do not get compilation errors. However, it does not do the job, and cannot differentiate between supply-0 and weak-0 .

I have the following:

module suputester(supu_io);
inout supu_io;

supply0 gnd;
supply1 vdd;

wire is_sp0 = (supu_io == gnd)? 1'b1: 1'b0;
wire is_sp1 = (supu_io == vdd)? 1'b1: 1'b0;
endmodule

An external module drives supu_io sequentially to supply-0, supply-1, weak-0, weak-1.
However, is_sp0 is 1 when supu_io is supply-0 or weak-0, and, similarly, is_sp1 is 1 when supu_io is supply-1 or weak-1.

Could anyone help me, please?

try

module suputester(supu_io);
inout supu_io;

supply0 gnd;
supply1 vdd;

wire is_sp0 = (supu_io == 1'b0)? 1'b1: 1'b0;
wire is_sp1 = (supu_io == 1'b1)? 1'b1: 1'b0;
endmodule


or try using CASEX

module suputester(supu_io);
inout supu_io;

supply0 gnd;
supply1 vdd;

wire is_sp0,is_sp1;

always@(*)
begin
casex(is_sp0)
1'b0 : is_sp0=1'b1;
default: is_sp0=1'b0;
endcase
casex(is_sp1)
1'b1 : is_sp1=1'b1;
default: is_sp1=1'b0;
endcase
end
endmodule


not sure if the syntax is 100% correct

on my second example.. it should be reg ofcourse not wire
reg is_sp0,is_sp1;

i want to have more information for the project "signed integer divider"
please help