I have two queries:
i- i want router 1X4 specification and/or its verilog code to carry out its verification using system verilog.
ii - Moreover,I have tried to verify small design say mod-9 counter using system verilog,but i am unable to introduce random delay between successive transaction. can any one help me out in this regard.normally delays can be inserted by using call backs and what are the other ways to do so?kindly give examples on that front.

thanks